The present invention relates to a semiconductor apparatus and a design apparatus and to, for example, a semiconductor apparatus capable of performing a variable compression scan test and a design apparatus for the semiconductor apparatus.
A common method of testing LSI (Large Scale Integration) is a scan test. In the scan test, a flip-flop (FF) in a circuit is replaced by an FF having a multiplexer (MUX) which is referred to as a scan FF. The MUX switches between a test input and normal operation input by a scan enable signal.
At the time of the scan test, scan FFs are serially connected to each other so that the scan FFs operate as a shift register (this is referred to as a “scan chain”) that can be controlled by an external input/output terminal of the LSI. By shifting the scan chain in response to a scan enable signal (this operation shall be referred to as a “scan shift operation”), an arbitrary test pattern is set in each scan FF.
Then, when the scan enable signal is switched, a value from the normal operation input is captured in the scan FF (this operation shall be referred to as a “capture operation”). The value captured in the capture operation is shifted again by the scan FF, and a response is observed (unload). At the same time as this unloading, the next test pattern is applied (load). The scan test is executed in this way.
In the scan test, as the number of necessary shift cycles corresponds to the number of the scan FFs that are connected to the scan chain, an extremely large number of test steps is required. A circuit having a large number of stages of the scan chain requires a long time for conducting the scan test, thus greatly influencing a cost of the test.
Japanese Unexamined Patent Application Publication No. 2004-77356 (Sannomiya) discloses a method of establishing a scan chain that reduces the number of test patterns for causing the scan chain to perform a shift operation. In the scan chain disclosed by Sannomiya, selectors for bypasses are inserted between a plurality of scan FFs. In this method of establishing a scan chain, the number of test patterns necessary for testing combinational circuits that are connected respectively to the plurality of scan FFs is calculated, and the plurality of scan FFs are grouped so as to correspond to the number of test patterns. When the scan FFs that are connected to the combinational circuits in which the test has been ended are bypassed by the unit of the groups, the shift operation is skipped and the number of test patterns is reduced.